The circuit and method of the above mentioned general type forming the field of this invention are known from the published European Patent application EP 0 993 122 A1. To generate a control voltage for controlling the voltage controlled oscillator (VCO), this European publication provides an adder circuit, which adds a predetermined frequency-dependent voltage to the output voltage of the loop filter. Those measures aim to reduce the transient settling time or frequency pull-in time of the circuit in connection with a change of the frequency.
Phase regulating circuits, and particularly phase locked loops (PLLs) are utilized, for example, to generate defined signals with frequency synthesizers for mixers. For this purpose in transceiver systems, it is necessary that the rated or nominal frequency of the PLL output signal can be sharply varied within a short time. Thus, for example, in the context of the GPRS (Global Packet Radio Services) standard, it is required that a frequency jump of about 150 MHz at an average or mid-frequency of about 2 to 2.4 GHz is carried out within about 150 to 200 μs. This time in which the frequency is switched to a new frequency (allowing for a transient to settle out to the new frequency) is referred to as the settling time. The accuracy with which the new nominal selected or desired frequency must be established within this settling time amounts to a few kHz.
The basic function of a phase regulating circuit and particularly a phase locked loop (PLL) involves dividing a reference frequency of, for example, 13 MHz by a factor R (typically 65) in a frequency divider. As a result, a frequency of about 200 kHz will be established at the output of the frequency divider. In the assumed example case of a GSM application, this frequency defines the channel raster prescribed by the system. Moreover, a second signal FVCO is generated by a voltage controlled oscillator (VCO) at a frequency of about 2 GHz. This second frequency signal is divided by a divisor N in a second frequency divider. By means of the regulating loop of the PLL including the charge pump and the loop filter, the flank of the divided signal of the VCO is regulated in such a manner so that the two input signals of the PLL have the same frequency and a fixed phase relationship. The two frequency dividers can be programmed via a serial interface, so that the frequency of the VCO can be adjusted, for example in 200 kHz steps, through an adjustment or variation of the divisor N by which the output signal of the VCO is divided.
With a comparison frequency of 200 kHz, a respective comparison is carried out every 5 μs. The loop filter must ensure that this 200 kHz interference only leads to a small or minor modulation of the voltage at the input of the voltage controlled oscillator (VCO). If this is not the case, spurious signals at a spacing of 200 kHz from the carrier frequency arise in the output spectrum of the VCO. It is typically required that these spurious signals are damped at greater than 60 dBc (decibels below carrier). The result thereof is that the bandwidth of the loop filter is normally limited to about 10 to 15% of the comparison frequency. For GSM applications, this means that the bandwidth is limited to about 20 to 30 kHz.
Simultaneously with limiting the bandwidth, the above damping of spurious signals also determines the settling time that is determinative of the transient frequency settling or pull-in of the PLL after a programmed frequency change. For frequency changes in the range from 100 MHz to 150 MHz, this means that a transient frequency settling or pull-in cannot be achieved within 200 μs if the bandwidth of the loop filter is about 20 kHz. This problem cannot be solved by increasing the filter bandwidth, because then the spurious signals can no longer be adequately and reliably suppressed.
In this context it is known to use a fractional PLL instead of an integer or integral PLL. However, a concept, e.g. a circuit arrangement and a method, with a fractional PLL requires special circuit measures for compensating so-called “fractional spurs”. In order to be able to further utilize the relatively simple concept of an integer PLL rather than a fractional PLL, National Semiconductor developed a so-called “FASTLOCK” architecture (LMX2330) in which the filter time constants are reduced at the beginning of the transient frequency settling or pull-in process of the PLL, in that a second resistor is temporarily connected parallel to a first resistor. In the final condition, the parallel resistor is again clamped off, so that the PLL once again operates with the normal small bandwidth.